1. Field of the Invention
The present invention relates to a manufacturing method of a semiconductor device having a circuit composed of a thin film transistor (hereafter, referred to as TFT), and in particular to a manufacturing method of a semiconductor device having a gate electrode wiring of a forwardly tapered shape which is obtained by photolithography processing and dry etching processing.
2. Related Art
Recently, electrooptical devices such as active matrix type liquid crystal display device, which performs active matrix display using a TFT, have been drawing public attention. The electrooptical device, which performs active matrix display, is provided with a TFT switch to each electrooptical device and state of crystal orientation of TN (abbreviation of Twisted-Nematic) mode can be utilized. Compared to a passive matrix display, since the active matrix display has advantages in the points of response speed, angle of visibility and contrast, it has become a major trend in the current notebook-sized personal computers, liquid crystal TVs and the like.
Generally, in the TFT, amorphous silicon or polycrystalline silicon is used as the channel layer thereof. Particularly, the polycrystalline silicon TFT, which is manufactured by means of low-temperature processing (generally, lower than 600xc2x0 C.), is in a trend of being reduced in price and being enlarged in size. Electron or positive hole of the polycrystalline silicon TFT has large electric field mobility. Accordingly, when the TFT is used in a liquid crystal display device, since it is possible to integrate not only the transistor for pixel but also the driver, which is a peripheral circuit thereof, each maker of liquid crystal display device has promoted its development. However, when the polycrystalline silicon TFT is driven for a long period of time, sometimes such problems concerning reliability that decrease of mobility or ON-current (current which flows when the TFT is ON), increase of OFF-current (current which flows when the TFT is OFF) or the like are found. These phenomena are called as hot carrier effect, and it is known that these phenomena are caused by hot carrier that is generated due to high electric field in the area adjacent to the drain.
On the other hand, in MOS transistor of 1.5 xcexcm in design rule, as a technique for buffering the OFF-current and the high electric field adjacent to the drain, an LDD (abbreviation of Lightly-Doped-Drain) structure is adopted. The LDD structure of NMOS transistor is formed by providing an n-type low-density impurity area (nxe2x88x92area) to the edge area of the drain using the side wall of the gate to provide a taper to the density of the impurity of the drain junction, and thereby, the concentration of electric field in the area adjacent to the drain is buffered. However, compared to the single drain structure, in the LDD structure, although the drain withstand voltage is considerably increased, since the resistance of the nxe2x88x92area is large, such disadvantage that drain current is decreased remains. Further, high electric field area exists under the side wall, the collision electrolytic dissociation reaches the maximum there, and hot electron is injected into the side wall. As a result, such problems of deterioration mode peculiar to the LDD that the nxe2x88x92area is depleted, and further, resistance is increased have emerged. Since the above-described problems have emerged accompanying the reduction of channel length, in the NMOS-transistor of 0.5 xcexcm or less, GOLD (abbreviation of Gate-Overlapped-LDD) structure, in which the nxe2x88x92area is formed being overlapped with the edge area of the gate electrode, has been developed as a structure for solving the problem, and is now promoted to put into the actual mass production.
Under such circumstances as described above, in the n-channel polycrystalline silicon TFT also, in order to buffer the high electric field in the area adjacent to the drain, it is considered to apply the GOLD structured TFT. For example, an example of the application of the GOLD structured TFT is disclosed in IEDM97 TECHNICAL DIGEST; P523-526, 1997; Mutuko Hatano, Hajime Akimoto and Takesi Sakai. In the above-described GOLD structured TFT, the side wall for LDD of the polycrystalline gate is formed with polycrystalline silicon, and in the active layer comprised of poly-crystalline silicon layer immediately under the side wall for LDD, a low-density impurity area(nxe2x88x92area), which functions as the electric field buffer area, is formed. Further, at the outside area of the low-density impurity area (nxe2x88x92area), a high-density impurity area (n+area), which functions as the source area and drain area, is formed. As described above, in the GOLD structured TFT, it is characterized by that the low-density impurity area (nxe2x88x92area) is formed being overlapped with the edge area of the gate electrode.
In the manufacturing method of a GOLD structured TFT, as for the method of forming the high-density impurity area (n+area) and the low-density impurity area (nxe2x88x92area), a method in which the impurity areas are formed with resist mask only; and another method in which, using the gate electrode as the mask, the impurity areas are formed in a manner of self-matching are known. In the former method in which the impurity areas are formed using the resist mask only, since the photolithography process for forming the resist mask is required to carry out twice, the increase in photolithography processes is a large disadvantage. On the other hand, in the latter method in which, using the gate electrode as the mask, the impurity areas are formed in a manner of self-matching, such an advantage that the photolithography process is prevented from increasing is provided, and that is advantageous for mass production processing.
As described above, in the polycrystalline silicon TFT, the GOLD structured TFT is taken into consideration. And as for the processing of the gate electrode of the GOLD structured TFT, the photolithography process using a positive type resist of diazonaphthoquinone (DNQ)-novolac resin series, which is generally used in semiconductor processing, and the etching process by means of dry etching are taken into consideration.
In the photolithography process using a positive type resist of diazonaphthoquinone (DNQ)-novolac resin series, as the preventive measures against halation phenomenon, conventionally, a method in which a photo-absorbent composed of dye is added to the resist material is known. The halation phenomenon is a phenomenon, in which the resist in unexposed area is locally exposed undesirably by the reflected light from the tapered shoulder portion of the high reflective base substrate resulting in a local thinness of the resist pattern. When adding the photo-absorbent to the resist material to prevent the halation phenomenon, if the added amount of the photo-absorbent is too small, the preventive effect against the halation phenomenon cannot be obtained satisfactorily. On the other hand, if the added amount of the photo-absorbent is too large, although the preventive effect against the halation phenomenon can be obtained satisfactorily, the absorbance of the resist material becomes too large resulting in such disadvantage that the taper angle of the side wall of the resist pattern decreases. Accordingly, when the photo-absorbent is added to the resist material as the preventive measures against the halation phenomenon, it is necessary to control the density of the photo-absorbent to an adequate level.
Referring to FIG. 5-F and FIG. 6-F showing an example of a GOLD structured TFT respectively, the GOLD structured TFT is constituted of a gate electrode which is comprised of a first layer gate electrode and a second layer gate electrode on the above-described first layer gate electrode. Compared to the second layer gate electrode, the first layer gate electrode is characterized in that it is formed thinner in film thickness and longer in dimension of the channel direction. The GOLD structured TFT is formed by laminating gate insulating film 203e, 303e respectively, being interposed by a semiconductor layer comprised of a polycrystalline silicon film on an insulative substrate such as a glass substrate or the like, and a first layer gate electrode 204e, 304e, which is thinner in film thickness and longer in dimension of the channel direction and a second layer gate electrode 205e, 305e, which is thicker in film thickness and shorter in dimension of the channel direction, are laminated thereon. And in the semiconductor layer, which is covered by the first layer gate electrode 204e, 304e, where is thin in film thickness and long in dimension in the channel direction, i.e., in the semiconductor layer corresponding to the area where the first layer gate electrode 204e, 304e is exposed from the second layer gate electrode 205e, 305e, an n-type low-density impurity area (nxe2x88x92area), which functions as the electric field buffer area, is formed so as to overlap with the gate electrode; and is named as Lov area 208, 309 respectively in FIGS. 5-F and 6-F. In the outside area of the Lov areas 208, 309, in the same manner as the above, an n-type low-density impurity area (nxe2x88x92area), which functions as the electric field buffer area, is formed so as not to overlap with the gate electrode; and is named as Loff areas 209, 310 respectively in FIGS. 5-F and 6-F. Furthermore, in the outside area of the Loff area 209, 310, an n-type high-density impurity area (n+area) 207, 307, which functions as the source area and drain area, is formed respectively (refer to FIGS. 5-F, 6-F).
In the GOLD structured TFT of n-type channel structured as described above, in order to increase the reliability of the GOLD structured TFT, it is preferred that the Lov area 208, 309, which overlaps with first layer gate electrode 204e, 304e, is longer. However, on the other hand, when the Lov area 208, 309 is too long, such disadvantage that the parasitic capacity increases remains. Accordingly, it is required to control the Lov area 208, 309 to an adequate dimension. The dimension of the Lov area 208, 309 is equal to that of the area where is covered by the first layer gate electrode 204e, 304e, i.e., the area where the first layer gate electrode 204e, 304e is exposed out of the second layer gate electrode 205e, 305e. Furthermore, the dimension of the Lov area 208, 309 is determined depending on the retreat amount of the resist pattern 206a, 306a in taper etching by means of resist-retreating method. Accordingly, to control the dimension of the Lov area 208, 309, it is necessary to control the retreat amount of the resist pattern 206a, 306a in taper etching, and it is known that the retreat amount of the resist is controlled by the taper angle of the side wall and the dry etching conditions of the resist pattern 206a, 306a, which is used as the mask in dry etching (refer to FIGS. 5-F, 6-F).
However, in the conventional configuration of the resist pattern 206a, 306a, the taper angle of the side wall of the resist pattern is larger than the desired taper angle in the range of 90xc2x0 or less. Accordingly, it is difficult to obtain a desired retreat amount of the resist unless the loss in quantity of the resist film is increased by setting the dry etching conditions to a severer level. Also, as a result, it is difficult to form the Lov area 208, 309 of desired dimension. On the other hand, when the dry etching conditions are set to a severer level, it is foreseeable that it works adversely with respect to the break of the gate insulating film in the GOLD structured TFT from the viewpoint of the processing margin. As described above, in the conventional technique, such problem remains that it is difficult to form the Lov area 208, 309 to a desired dimension from the viewpoint of the processing margin (refer to FIGS. 5-F, 6-F).
An object of the invention is to solve the above-described problems of the conventional technique, more particularly, to solve the problems with respect to the processing margin in forming the Lov area of a GOLD structured TFT.
[Consideration on Taper Angle of the Side Wall of the Resist Pattern]
First of all, the relationship between the dimension of the Lov area of the above-described GOLD structured TFT and the angle of the side wall of the resist pattern taper, which is used as the dry etching mask for the gate electrode, will be described. FIG. 1 is a graph of data representing correlation between the taper angle of the side wall of a resist pattern and the dimension of the Lov area of a GOLD structured TFT. Based on FIG. 1, it is understood that there is a strong correlation (correlation coefficient: r=xe2x88x920.889) between the taper angle of the side wall of the resist pattern and the dimension of the Lov area. In the experiment from which the data of FIG. 1 was obtained, in order to determine the taper angle of the side wall of the resist pattern, resist patterns after being subjected to post-baking (approximately 120xc2x0 C.) are subjected to a baking treatment within a temperature range of 160-200xc2x0 C. in an oven bake furnace to form resist patterns having various taper angle of the side wall. As for the resist patterns after being subjected to the baking treatment in the oven bake furnace, since the baking treatment was made at a resist softening temperature higher than the glass transition temperature of the resist material, the resist pattern was softened by heat resulted in a warp on the side wall. Therefore, it was difficult to correctly measure the taper angle of the side wall. Accordingly, the taper angle of the side wall of the resist patterns was obtained as below; i.e., the distance between the side wall corresponding to a height of 1 xcexcm from the bottom of the resist pattern and the edge of the resist pattern was linearly approximated, and the angle which was made by the straight line and the base substrate was defined as taper angle of the side wall, and the correlation data in FIG. 1 was obtained.
Based on FIG. 1, to control the dimension of the Lov area, it is revealed that the control of the taper angle of the side wall of the resist pattern is indispensable. In the experiment where the data of FIG. 1 was obtained, in order to change the taper angle of the side wall of the resist pattern, since the baking treatment was carried out at a resist softening temperature higher than the glass transition temperature, such disadvantage that the resist pattern flows due to heat and the side wall of the resist pattern warps remains. Accordingly, in the method by which the baking treatment is carried out at a resist softening temperature higher than the glass transition temperature, since such disadvantage that the dimensional dispersion of the Lov area becomes large remains, the method is not appropriate for mass production processing. Accordingly, it was determined to examine a method other than resist softening by means of baking treatment, by which the taper angle of the side wall of the resist pattern can be made smaller stably.
For forming the resist pattern, a resist pattern composed of a positive type resist of diazonaphthoquinone (DNQ)-novolac resin series, which is generally used in semiconductor processing, is adopted. The resist pattern is formed by means of the photolithography process, which is comprised of the following steps; i.e., xe2x80x9cresist coatingxe2x80x9dxe2x86x92xe2x80x9cpre-bake (approximately 90xc2x0 C.)xe2x80x9dxe2x86x92xe2x80x9cexposurexe2x80x9dxe2x86x92xe2x80x9cpost-exposure baking (approximately 120xc2x0 C.)xe2x80x9dxe2x86x92xe2x80x9cexposurexe2x80x9dxe2x86x92xe2x80x9cpost bake (approximately 120xc2x0 C.)xe2x80x9d. The foregoing post-exposure baking is a step adopted to prevent interference pattern which appears on the side wall of the exposed resist pattern when the exposure is carried out using a single wavelength (for example, g-ray or i-ray of an extra-high voltage mercury-vapor lamp; equivalent to a compaction project exposure apparatus). Accordingly, when the exposure is carried out using, not a single wavelength exposure but a plurality of exposure wavelengths (for example, g-ray, h-ray and i-ray of an extra-high voltage mercury-vapor lamp; equivalent to an ordinary 100% magnification exposure apparatus), since the above-described interference pattern does not occur, there may be a case that the step is not adopted.
As described above, although the dimension of the Lov area depends on the taper angle of the side wall of the resist pattern, however, in actual fact, in addition to the taper angle of the side wall of the resist pattern, the dimension thereof depends also on the dry etching conditions. As the dry etching conditions, taper etching by means of resist-retreating technique, in which dry etching is carried out while the resist pattern is retreated, is adopted. In the taper etching methods, as a technique thereby the retreat amount of the resist is promoted by promoting retreat of the resist pattern, the techniques, in which oxygen (O2) is added to the dry etching gas or the bias power is increased, are known.
Under the circumstances as described above, in order to obtain a desired dimension of the Lov area, it is necessary to make the taper angle of the side wall of the resist pattern smaller from the view point of the processing margin. Therefore, the invention proposes, as a technique by which the taper angle of the side wall of the resist pattern is made smaller, a technique by which the photo-absorbency of the resist film with respect to the exposure light is increased by adding a photo-absorbent, which is a kind of dye, to the resist material, which is composed of a positive type resist of diazonaphthoquinone (DNQ)-novolac resin series. As for the resist containing photo-absorbent in which the resist material is added with photo-absorbent, although it is a conventionally well-known technique as a preventive measure against the halation phenomenon, according to the invention, the photo-absorbent is added into the resist material for the purpose of making the taper angle of the side wall of the resist pattern smaller.
FIG. 2-A is a diagram of the data representing the relationship between the distance from the resist surface and the light intensity of the exposure light when the exposure light strikes thereon from the surface of the resist, in which a mode of exponentially decay of the light intensity of the exposure light with respect to the resist surface is represented. Defining the initial light intensity of the exposure light is I0; the light intensity of the exposure light at a point d away from the surface of the resist film is I; and the absorbance degree of the resist per unit film thickness is xcex1; the decay curve of the light intensity is expressed by a relational expression: I=I0exp[xcex1xe2x88x92d], which is well known as the law of Lambert. In this relational expression, a is a constant peculiar to the resist material and the wavelength. When the photo-absorbent is added to the resist material, in the decay curve of the light intensity I=I0exp[xe2x88x92xcex1d], the value of xcex1, which represents the absorbance per unit film thickness, becomes larger, the light intensity of the exposure light decays sharply with respect to the distance from the resist surface.
Since the further sharp decay of the exposure light leads to a decrease of the exposure energy, which arrives at the lower layer of the resist pattern, compared to the upper layer, relatively, the dimension of the resist pattern becomes larger. As a result, it is understood that the taper angle of the side wall of the resist pattern becomes smaller. Also, since the absorbance degree xcex1 per unit film thickness of the photo-absorbent depends on the density, it is understood that when the density of the photo-absorbent is determined, only one value of the absorbance degree xcex1 is also determined. Accordingly, by controlling the density of the photo-absorbent in the positive type resist containing the photo-absorbent, since it is possible to control the absorbance degree xcex1 per unit film thickness, it becomes possible to control the mode of the decay of the exposure energy which reaches the lower layer of the resist film. As a result, it is understood that it becomes possible to strictly control the taper angle of the side wall of the resist pattern. FIG. 2-B shows an example of configuration of the resist pattern in the case that the absorbance degree xcex1 per unit film thickness of the resist is large and the case that the same is small. It shows schematically that, in the case that the absorbance degree xcex1 is small, the taper angle of the side wall xcex81 becomes larger; and in the case that the absorbance degree xcex1 is large, the taper angle of the side wall xcex82 becomes smaller (refer to FIG. 2).
FIG. 3 is an example of graphs representing the data of the transmittance spectrum of a positive type resist of diazonaphthoquinone (DNQ)-novolac resin series before/after exposure. FIG. 3-A shows the data of the transmittance spectrum in the case that the photo-absorbent is not added; FIG. 3-B shows the data of the transmittance spectrum in the case that the photo-absorbent is added. Referring to FIG. 3, without depending on whether or not is added, in the transmittance spectrum of the unexposed resist, a sharp decrease of the transmittance is found in the range of 300-450 nm of wavelength range. On the other hand, in the transmittance spectrum of the exposed resist, a sharp decrease of the transmittance is not found in the range of 300-450 nm of wavelength range. In this range of the wavelength, since the transmittance increases owing to the exposure, the reason why the transmittance of the unexposed resist is low in this range of wavelength is caused from the photo-absorbency of the photo-absorbent of the diazonaphthoquinone series. When the photo-absorbent is added to the resist material, which has the transmittance spectrum property as described above, in both of the unexposed resist and the exposed resist, the transmittance decreases in the range of 300-500 nm of wavelength. As for the reason why the transmittance decreases before/after the exposure in both cases thereof, it is understood that since the photo-absorbency of the photo-absorbent component does not accompany any photochemical reaction, there is little changes in the state of the photo-absorbency before/after the exposure. Accordingly, when the exposure light is irradiated to the resist film containing the photo-absorbent, the photo-absorbency of the photo-absorbent of the diazonaphthoquinone series is lost in accordance with the progress of the photochemical reaction, the novolac resin component, which is the base resin, and the photo-absorbent component are the major source of the photo-absorbency of the exposed resist film.
By adding the photo-absorbent to the resist material, it is possible to decrease the transmittance in the range of 300-500 nm of wavelength in the transmittance spectrum before/after the exposure; i.e., it is possible to make the absorbance degree xcex1 in the foregoing wavelength range larger. In this case, since the absorbance degree xcex1 in the foregoing wavelength range, precisely describing, varies depending on the wavelength, it is expected that the taper angle of the side wall of the resist pattern varies depending on the exposure wavelength of the exposure apparatus. For example, as for the exposure wavelength of the compaction project exposure apparatus, a single wavelength of g-ray (436 nm) or i-ray (365 nm) of an extra-high voltage mercury-vapor lamp is adopted. On the other hand, the exposure wavelength of the projection exposure apparatus, which is a 100% magnification exposure apparatus, a multi-wavelength comprised of g-ray (436 nm), h-ray (405 nm) and i-ray (365 nm) of the extra-high voltage mercury-vapor lamp is adopted. As described above, since the exposure wavelength varies depending on the exposure apparatus, even when a resist containing photo-absorbent of the same density of the photo-absorbent is used, it is expected that the taper angle of the side wall of the resist pattern may vary. Accordingly, it is necessary to optimize the type of the photo-absorbent and amount thereof, which is added to the resist material, depending on the type of the exposure apparatus. Further, since the taper angle of the side wall of the resist pattern is subjected to the influence of the projecting optical system of the exposure apparatus, it is understood that it is necessary to optimize the type of the photo-absorbent and amount thereof, which is added to the resist material, depending on the type of the exposure apparatus.
The photolithography technique, which uses a positive type resist containing photo-absorbent, is conventionally known as a preventive measures against the halation phenomenon. Hereafter, as a reference, referring to FIG. 4, preventive mechanism against the halation phenomenon by the positive type resist containing photo-absorbent will be described. FIG. 4 is a schematic view illustrating preventive mechanism against the halation phenomenon; FIG. 4-A is a sectional view of a portion where the halation occurs; FIG. 4-B is a plane view of a portion where the halation occurs. The sectional view of FIG. 4-A is a sectional view along the line A-Axe2x80x2 of FIG. 4-B.
The halation phenomenon is a phenomenon, in which exposure light transmitted through a quartz substrate 101 of a photo mask or a reticle reflects on a tapered shoulder portion 103 of a high-reflective substrate, and the resist film in a portion shielded by a light shielding film mask pattern 102 disposed on the quartz substrate 101 to prevent the film from being exposed is undesirably exposed by the foregoing reflected light. Due to this halation phenomenon, the undesirably exposed portion 104 is melted during developing processing; and as a result, a resist pattern 105, from which the undesirably exposed portion 104 is lost, is formed. Also, when the resist pattern 105, from which the undesirably exposed portion 104 is lost, is observed from the top, the resist pattern 105, which has a locally thin portion due to the lose of the undesirably exposed portion 104, is formed. The locally thin portion often produced, particularly, in a portion where the reflected light from the tapered shoulder portion 103 is focused (refer to FIG. 4).
In a portion where a halation phenomenon as described above occurs, defining the distance from the resist surface 106 to the tapered shoulder portion 103 is d1; the distance between the tapered shoulder portion 103 and the undesirably exposed portion 104 is d2; and assuming that exposure light is reflected by 100% on the tapered shoulder portion 103; the light intensity of the reflected light, which reaches the undesirably exposed portion 104, is expressed by a relational expression: I=Ioexp[xe2x88x92xcex1(d1+d2)]. Accordingly, by making the absorbance degree xcex1 per unit film thickness of the resist larger, or by making the distance d2 between the tapered shoulder portion 103 and the undesirably exposed portion 104 larger, it is possible to reduce the light intensity of the reflected light, which reaches the undesirably exposed portion 104. As for the technique in which the distance d2 between the tapered shoulder portion 103 and the undesirably exposed portion 104 is made larger, it means that the every circuit pattern at the portion where the halation occurs requires change of design. Accordingly, it is difficult to carry out the technique from the viewpoint of workability. On the other hand, as for the technique in which the absorbance degree xcex1 per unit film thickness of the resist is made larger, since it is easy to carry out by adding a photo-absorbent to the resist material, it has been put into practical use as a convenient preventive measures against the halation phenomenon (refer to FIG. 4).
For the purpose of prevention of the foregoing halation phenomenon, generally, a minimum amount of photo-absorbent necessary to prevent the halation phenomenon is added. The reason of this is that, if the added amount of the photo-absorbent is too excessive, although the halation phenomenon can be reliably reduced, such a disadvantage that the taper angle of the side wall of the resist pattern becomes smaller. The object of the invention is to make the taper angle of the side wall of the resist pattern smaller, and to aggressively use the fact that the taper angle of the side wall of the resist pattern becomes smaller by adding excessive photo absorbent. Accordingly, the major aim of the invention is, by controlling the density of the photo-absorbent of the positive type resist, which contains a photo-absorbent of diazonaphthoquinone (DNQ)-novolac resin series, to control the taper angle of the side wall of the resist pattern to a desired taper angle, and thereby to control the dimension of the Lov area of the GOLD structured TFT having a gate electrode of double-layered structure, of which first layer gate electrode is, compared to the second layer gate electrode, thinner in film thickness and longer in dimension of the channel direction, to a desired dimensional range.
[Manufacturing Method of Semiconductor Device]
A solving means of the above-described problems will be described hereafter from the viewpoint of the manufacturing method of semiconductor device.
The constitution of the invention is characterized in that a method of producing a semiconductor device includes the steps of:
forming a resist pattern composed of a positive type resist, which contains a photo-absorbent of diazonaphthoquinone (DNQ)-novolac resin series, on a coating formed on an insulating substrate; and
etching the coating using the resist pattern, wherein the density of the photo-absorbent contained in the positive type resist, which contains the photo-absorbent, is controlled, the taper angle of side wall of the resist pattern is set to a predetermined taper angle and the dimension of a tapered area of an etching pattern is set to a predetermined dimension.
The constitution of the invention is characterized in that a method of producing a semiconductor device, comprising the steps of:
forming a semiconductor layer on an insulating substrate;
forming a gate insulating film on the semiconductor layer;
forming a first layer gate electrode on the gate insulating film;
forming a second layer gate electrode on the first layer gate electrode;
forming a resist pattern composed of a positive type resist, which contains a photo-absorbent of diazonaphthoquinone (DNQ)-novolac resin series, on the second layer gate electrode;
forming a first shaped gate electrode by subjecting the first layer gate electrode and the second layer gate electrode to dry etching using the resist pattern as a mask;
forming a first impurity area by injecting a single-conductive impurity element into the semiconductor layer using the first shaped gate electrode as a mask;
forming a second shaped gate electrode in which the first layer gate electrode is longer than the second layer gate electrode in dimension of the channel direction by subjecting the first shaped gate electrode to dry etching using the resist pattern as a mask; and
forming a second impurity area positioned under the first layer gate electrode and a third impurity area sandwiched between the first impurity area and the second impurity area by injecting the impurity element into the semiconductor layer using the second shaped gate electrode as a mask, wherein the density of the photo-absorbent contained in the positive type resist, which contains the photo-absorbent, is controlled, taper angle of side wall of the resist pattern is set to a predetermined taper angle and the dimension in the channel direction of the second impurity area is set to a predetermined dimension.
The constitution of the invention is characterized in that a method of producing a semiconductor device, comprising the steps of:
forming a semiconductor layer on an insulating substrate;
forming a gate insulating film on the semiconductor layer;
forming a first layer gate electrode on the gate insulating film;
forming a second layer gate electrode on the first layer gate electrode;
forming a resist pattern composed of a positive type resist, which contains photo-absorbent of diazonaphthoquinone (DNQ)-novolac resin series, on the second layer gate electrode;
forming a first shaped gate electrode by subjecting the first layer gate electrode and the second layer gate electrode to dry etching using the resist pattern as a mask;
forming a first impurity area by injecting a single-conductive impurity element into the semiconductor layer using the first shaped gate electrode as a mask;
forming a second shaped gate electrode in which the first layer gate electrode is longer than the second layer gate electrode in dimension of the channel direction by subjecting the first shaped gate electrode to dry etching using the resist pattern as a mask;
forming a second impurity area positioned under the first layer gate electrode and a third impurity area sandwiched between the first impurity area and the second impurity area by injecting the impurity element into the semiconductor layer using the second shaped gate electrode as a mask; and
forming a third shaped gate electrode by selectively subjecting the first layer gate electrode included by the second shaped gate electrode to etching, wherein the density of photo-absorbent contained in the positive type resist, which contains the photo-absorbent, is controlled, the taper angle of side wall of the resist pattern is set to a predetermined taper angle and the dimension of the second impurity area in the channel direction overlapped with the third shaped gate electrode is set to predetermined dimension.
The invention having the above-described constitution controls the density of the photo-absorbent that is contained in the resist pattern for forming the gate electrode composed of the positive type resist which contains a photo-absorbent of diazonaphthoquinone (DNQ)-novolac resin series. By controlling the density of the photo-absorbent, the absorbance of the resist with respect to the exposure light is controlled so as to become larger. In other words, the transmittance of the resist with respect to the exposure light is controlled so as to become smaller. Accordingly, owing to the control of the density of the photo-absorbent, since it is possible to obtain a sharp decay of the intensity of the exposure light, it is possible to reduce the exposure energy that reaches the lower layer of the resist pattern. Owing to this, the exposure energy for the upper layer of the resist pattern can be controlled to be larger, and compared to the upper layer, the exposure energy for the lower layer of the resist pattern can be controlled to be smaller. As a result, it is possible to make the dimension of the lower layer of the resist pattern, compared to the upper layer, relatively larger. That is to say, owing to the control of the density of the photo-absorbent, it is possible to control the taper angle of the side wall of the resist pattern so as to become smaller.
According to the constitution of the invention, the taper angle of the side wall of the resist pattern for forming a gate electrode can be controlled so as to become smaller. Owing to this, even when the loss in quantity of the resist film during dry etching is small, a desired retreat amount of the resist can be obtained relatively easily. Owing to this, it is understood that, in a taper etching of a single-layer film by means of resist-retreating method, the dimension of the tapered area can be easily controlled within a desired dimensional range so as to become larger.
According to the constitution of the invention, the taper angle of the side wall of the resist pattern for forming a gate electrode can be controlled so as to become smaller. Owing to this, even when the loss in quantity of the resist film during dry etching is small, a desired retreat amount of the resist can be obtained relatively easily. Owing to this, in the foregoing second shaped gate electrode, the dimension of the exposed first layer gate electrode in the channel direction can be set to a predetermined dimension. Accordingly, the dimension of the foregoing second impurity area in the channel direction corresponding to the exposed first layer gate electrode can be set to a predetermined dimension.
According to the constitution of the invention, the taper angle of the side wall of the resist pattern for forming a gate electrode can be controlled so as to become smaller. Owing to this, even when the loss in quantity of the resist film during dry etching is small, a desired retreat amount of the resist can be obtained relatively easily. Owing to this, in the foregoing second shaped gate electrode, it is possible to set the dimension of the channel direction of the exposed first layer gate electrode, i.e., the dimension in the channel direction of the foregoing second impurity area to a predetermined dimension. Accordingly, it is possible to set the dimension in the channel direction of the area where the foregoing third shaped gate electrode overlaps with the foregoing second impurity area to a predetermined dimension.